1. Field of the Invention
The present invention relates to a semiconductor device and, in particular, to a power semiconductor device contained in a power integrated circuit device.
2. Description of the Background Art
A power integrated circuit device (a power IC or HVIC: high voltage IC), in which power semiconductor devices and logical circuits are integrated on one chip, is indispensable to achieve high performance and low cost in the field of mechatronics such as motor control.
Especially in performing bridge rectification of a power line, a P channel LHVMOS (lateral high voltage MOS) transistor and a P channel DAD (dual action device) are usually used for a high side level shift device that transfers a signal (high side signal) sent from a high side (high potential) circuit to a low side (low potential) circuit.
The P channel DAD has such a structure that a P channel LHVMOS transistor and an N channel LHVMOS transistor are integrally formed, and has the characteristic of being able to improve on state current density five times the P channel LHVMOS (Reference material: xe2x80x9cAn 0.8 xcexcm High-Voltage IC Using a Newly Designed 600-V Lateral P-Channel Dual-Action Device on SOIxe2x80x9d, by K. Watabe et al., IEEE Journal of Solid-state circuits, vol. 33, No. 9, September 1998).
FIG. 30 illustrates a plan configuration of a conventional P channel DAD 900. FIG. 31 illustrates a sectional configuration taken along the line Axe2x80x94A in FIG. 30.
Referring to FIG. 30, the P channel DAD 900 has at its midportion a linear source electrode 109, the periphery of which is surrounded by a first gate electrode 110. Further, the periphery of the first gate electrode 110 is surrounded by a second drain electrode 113, second gate electrode 111 and first drain electrode 112 in the order named. Every electrode is of an elongated annulus ring.
A source wiring SL, first gate wiring G1, second drain wiring D2, second gate wiring G2 and first drain wiring D1 are connected to the source electrode 109, first gate electrode 110, second drain electrode 112, second gate electrode 111 and first drain electrode 112, respectively.
The second drain wiring D2 is electrically connected via a resistance R1 to the second gate wiring G2, and the second gate wiring G2 is electrically connected via a resistance R2 to the first drain wiring D1.
Referring now to FIG. 31, a sectional configuration of the P channel DAD 900 will be described. The P channel DAD 900 is formed on a SOI substrate in which a buried oxide film 101 and a SOI layer 102 having a relatively low concentration of an N type impurity (i.e., Nxe2x88x92) are disposed on a support substrate 100 such as a silicon substrate.
Looking from the lefthand of FIG. 31, a P type well region 1031, a P type well region 1032 and an N type well region 104 are disposed in the surface of the SOI layer so that these regions are isolated from one another. Between the P type well region 1032 and N type well region 104, a P type drain region 107 having a relatively low concentration of a P type impurity (i.e., Pxe2x88x92) is formed so as to be continuous with the P type well region 1032. The P type drain region 107 is formed at a shallower position than the P type well region 1032.
Looking from the lefthand of FIG. 31, a P type diffusion region 1051 having a relatively high concentration of a P type impurity (i.e., P+) and an N type diffusion region 1061 having a relatively high concentration of an N type impurity (i.e., N+) are disposed adjacent each other in the surface of the P well region 1031. Looking from the righthand of FIG. 31, an N type diffusion region 1062 (i.e., N+) and a P type diffusion region 1052 (i.e., P+) are disposed adjacent each other in the surface of the N type well region 104.
Disposed on a first main surface of the SOI layer 102 are first and second drain electrodes 112, 113 and a source electrode 109. The first drain electrode 112 is formed in contact with the upper surface of the P type diffusion region 1051 and N type diffusion region 1061 in order to cause a short-circuit therebetween. The second drain electrode 113 is formed in contact with the upper surface of the P type well region 1032. The source electrode 109 is formed in contact with the upper surface of the P type diffusion region 1052 and N type diffusion region 1062 in order to cause a short-circuit therebetween.
As an insulating gate electrode, a first gate electrode 110 is disposed so as to cover the area from the upper surface of the peripheral portion of the P type drain region 107, the upper surface of the SOI layer 102 (between the P type drain region 107 and N type well region 104), the upper surface of the N type well region 104, and to the upper surface of the peripheral portion of the P type diffusion region 1052. A second gate electrode 111 is disposed so as to cover the area from the upper surface of the peripheral portion of the N type diffusion region 1061, the upper surface of the P type well region 1031, the upper surface of the SOI layer 102 (between the P type well region 1031 and P type well region 1032), and to the upper surface of the peripheral portion of the P type diffusion region 1032. A gate insulating film GX is present between the SOI layer 102 and the first gate electrode 110 or the second gate electrode 111.
A back side electrode 114 is formed over the entire surface of a second main surface of the support substrate 100, and the back side electrode 114 is usually connected to a ground potential.
Description will now be given of operation.
Off state (a forward blocking state) is realized by that the first drain electrode 112 and back side electrode 114 are connected to a ground potential in order to cause a short-circuit therebetween, a power source voltage is applied to the source electrode 109 to obtain a positive potential, and the first gate electrode 110 is connected to the source electrode 109 in order to cause a short-circuit therebetween. Note that the second gate electrode G2 is free (i.e., no control signal is provided from the exterior) under off state and also on state operation to be described later.
On state is realized by controlling the potential of the first gate electrode 110 to the minus side with respect to the source electrode 109. That is, by making the potential of the first gate electrode 110 lower than that of the source electrode 109, a P type channel is formed in the surface of the N type well region 104 and SOI layer 102 which are located immediately below the first gate electrode 110, and holes are therefore injected from the P type diffusion region 1052 to the P type drain region 107. This is the same operation as in a usual lateral P channel MOS transistor.
The holes injected to the P type drain region 107 pass through the second drain electrode 113 to the first drain electrode 112 via the resistances R1 and R2. During this, when the potential difference occurred in the resistances R1 and R2 becomes a predetermined value, the second gate electrode 111 functions as a gate, and an N type channel is formed in the surface of the P type well region 1031 immediately underlying the second gate electrode 111.
As a result, electrons are injected from the N type diffusion region 1061 to the SOI layer 102, and the injected electrons then reach the source electrode 109 via the N type well region 104 and N type diffusion region 1062. This is the same operation as in a lateral N channel MOS transistor.
Thus, the P channel DAD is a device in which the lateral P channel MOS transistor and the lateral N channel MOS transistor are combined to form a monolithic structure, and has the advantage of reducing on state resistance because the first gate electrode 110 is controlled by a power source side signal (high side signal) and the N channel MOSFET operates in on state.
However, in this conventional P channel DAD 900 so constructed, it is inherent to contain a P/N/P/N structure made up of the P type diffusion region 1052, N type well region 104, SOI layer 102, P type well region 1031 and N type diffusion region 1061. When a parasitic thyristor formed by the P/N/P/N structure is brought into on state, the device results in a latch-up state and goes out of control.
FIG. 32 illustrates an equivalent circuit of the P channel DAD 900. In FIG. 32, the emitter of an NPN type transistor Q3 is connected to the source of a P channel MOS transistor Q1, the collector of the NPN type transistor Q3 is connected to the base of a PNP type transistor Q4, the collector of the PNP type transistor Q4 is connected to the base of the NPN type transistor Q3, the emitter of the PNP type transistor Q4 is connected to the drain of the N channel MOS transistor Q2, and a thyristor parasitizes between the source (S) and drain (D) of the P channel DAD 900.
When this construction is subjected to a high density injection of electrons and holes, it might cause a modulation and lead to a latch-up state.
According to a first aspect of the present invention, a semiconductor device comprises first and second MOS transistors having different conductive types of which main current flows in a lateral direction and being disposed on a SOI substrate constructed by having on a support substrate a buried oxide film and a SOI layer, wherein the potential of a control electrode of the second MOS transistor is controlled according to a potential based on the main current of the first MOS transistor, to control on-off operation of the second MOS transistor, the semiconductor device further comprising in the SOI layer an isolation structure for electrically isolating the first and second MOS transistors in order to cut off a passage through which the main current of the first MOS transistor passes a region for forming the second MOS transistor and flows into a first main electrode of the second MOS transistor.
According to a second aspect of the invention, (i) the first MOS transistor comprises: a first main electrode having a linear shape in plan configuration; a linear shape control electrode having a length not exceeding the length of the first main electrode and being disposed parallel to the first main electrode; and a linear shape second main electrode having the same length as the control electrode and being disposed parallel to the control electrode, (ii) the first main electrode of the second MOS transistor has a plan configuration of an elongated annulus ring surrounding, as its midportion, the first main electrode of the first MOS transistor and enclosing the first MOS transistor, the second MOS transistor comprising: a control electrode disposed along the inside of the elongated annulus ring; and a second main electrode provided in common to the first main electrode of the first MOS transistor, (iii) the isolation structure comprises: isolation regions disposed on both ends of the control electrode and both ends of the second main electrode of the first MOS transistor, so as to extend, between one ends and the other ends of the control electrode and the second main electrode of the first MOS transistor, (iv) the isolation regions comprise: plural trenches of which contour is defined by an impurity region for PN junction isolation, and which are disposed in the impurity region and reach the buried oxide film constituting the SOI substrate, and (v) the plural trenches are arranged in at least one line from the first main electrode to the second main electrode of the first MOS transistor, each of the plural trenches having: an inner wall oxide film covering the inner wall; and a conductor buried in a region surrounded by the inner wall oxide film.
According to a third aspect of the invention, the semiconductor device further comprises: plural multi-field plates disposed coaxially around the first main electrode of the first MOS transistor on an upper portion of the SOI layer that is provided inside the first main electrode of the second MOS transistor, wherein a trench width and a trench interval along the direction of array of the plural trenches are set so as to substantially match a plate width and a plate interval along the direction of array of the multi-field plates.
According to a fourth aspect of the invention, (i) the first MOS transistor comprises: a first main electrode being at the center of a coaxial structure; a control electrode surrounding the first main electrode; and a second main electrode surrounding the control electrode, (ii) the second MOS transistor comprises: the first main electrode being at the outermost periphery of coaxial structure; a second main electrode being at the center of coaxial structure; and a control electrode disposed along the inside of the first main electrode, (iii) the isolation structure comprises: a first trench isolation wall reaching the buried oxide film and being disposed in the SOI layer so as to surround the first MOS transistor; and a second trench isolation wall reaching the buried oxide film and being disposed in the SOI layer so as to surround the second MOS transistor, each of the first and second trench isolation walls having: an inner wall oxide film covering the inner wall; and a conductor buried in a region surrounded by the inner wall oxide film.
According to a fifth aspect of the invention, (i) the first MOS transistor comprises: a first main electrode being at the outermost periphery of a coaxial structure; a control electrode disposed along the inside of the first main electrode; and a second main electrode being at the center of the coaxial structure, (ii) the second MOS transistor comprises: a first main electrode being at the outermost periphery of coaxial structure; a second main electrode being at the center of coaxial structure; and a control electrode disposed along the inside of the first main electrode, (iii) the isolation structure comprises: first and second trench isolation walls reaching the buried oxide film and being disposed in the SOI layer so as to surround a high side region of a relatively high potential and the second MOS transistor, each of the first and second trench isolation walls having: an inner wall oxide film covering the inner wall; and a conductor buried in a region surrounded by the inner wall oxide film, and the first MOS transistor being disposed in the high side region.
According to a sixth aspect of the invention, (i) the first MOS transistor comprises: a first main electrode having a linear shape in plan configuration; a linear shape control electrode disposed parallel to the first main electrode and having a length not exceeding the length of the first main electrode; and a linear shape second main electrode disposed parallel to the control electrode and having the same length as the control electrode, (ii) the second MOS transistor comprises: the first main electrode being at the outermost periphery of a coaxial structure; a second main electrode being at the center of the coaxial structure; and a control electrode disposed along the inside of the first main electrode, (iii) the isolation structure comprises: first and second trench isolation walls reaching the buried oxide film and being disposed in the SOI layer so as to surround a high side region of a relatively high potential and the second MOS transistor, the first MOS transistor being disposed in the high side region, each of the first and second trench isolation walls having: an inner wall oxide film covering the inner wall; and a conductor buried in a region surrounded by the inner wall oxide film, the first trench isolation wall having: side surface isolation walls disposed on both end portions of the first main electrode, the control electrode and the second main electrode of the first MOS transistor, so as to extend between one end portions and between the other end portions of the first main electrode, the control electrode and the second main electrode of the first MOS transistor; and first and second isolation walls disposed outside of the first and second main electrodes of the first MOS transistor, and the first MOS transistor being surrounded by the side surface isolation walls and the first and second isolation walls.
According to a seventh aspect of the invention, the side surface isolation walls have: plural trenches disposed at a predetermined interval so as to be parallel to each electrode of the first MOS transistor, each of the trenches having: the inner wall oxide film; and the conductor buried in a region surrounded by the inner wall oxide film, and each one end of the plural trenches being arranged along the peripheral portion of the region for forming the first MOS transistor.
According to an eighth aspect of the invention, the side surface isolation walls have: plural first trenches arranged at predetermined interval so as to be parallel to each electrode of the first MOS transistor; and plural second trenches of a rectangle shape in plan configuration disposed at the peripheral portion of the array of the plural first trenches, each of the plural first and second trenches having: the inner wall oxide film; and the conductor buried in the region surrounded by the inner wall oxide film, each one end of the plural first trenches being arranged along the peripheral portion of the region for forming the first MOS transistor, the plural second trenches being disposed so as to block the end portion of the SOI layer among the plural first trenches, the inner wall oxide film of the plural first trenches and the inner wall oxide film of the plural second trenches being joined and integral with each other.
According to a ninth aspect of the invention, the second main electrode of the first MOS transistor is connected via a first resistance component to the control electrode of the second MOS transistor, and the control electrode of the second MOS transistor is connected via a second resistance component to the first main electrode of the second MOS transistor.
In the semiconductor device of the first aspect, the isolation structure is provided in order to prevent that the main current of the first MOS transistor flows through the region for forming the second MOS transistor to the first main electrode. Therefore, holes and electrons that are carriers constituting the main current of the first and second MOS transistors are isolated from each other by the isolation structure. This enables to suppress an occurrence of modulation thereby to prevent latch-up of parasitic thyristor even if hole and electrons are obtained at a high density.
In the semiconductor device of the second aspect, at least a plurality of trenches aligned in a line are disposed from the first main electrode side to the second main electrode side of the first MOS transistor in the impurity region for PN junction isolation of the isolation region, in such a shape that the first MOS transistor is included in the region for forming the second MOS transistor. Therefore, when a forward blocking voltage is applied, the field occurred between the first and second main electrodes passes and distributes via the inner wall oxide film of each trench. Thereby, each trench can bear its proportionate share of the total field and the field concentration in the isolation region can be relaxed to stabilize breakdown voltage characteristic.
In the semiconductor device of the third aspect, the trench width and trench interval along the direction of array of plural trenches are set so as to substantially match the plate width and plate interval along the direction of array of multi-field plates. Therefore, the field distribution distributed by the trenches is also maintained by the multi-field plates, and the field concentration in the isolation region can be further relaxed in combination of the multi-field plates.
In the semiconductor device of the fourth aspect, the first and second MOS transistors are disposed so that these are isolated from each other, and these transistors are electrically isolated by the first and second trench isolation walls. Therefore, holes and electrons that are carriers constituting the main current of the first and second MOS transistors are isolated from one another by the isolation structure, and an occurrence of modulation can be suppressed even if holes and electrons are obtained at a high density. In addition, since the first and second MOS transistors are isolated for electrical isolation, no parasitic thyristor structure is present and latch-up can be principally prevented to allow for an improvement in resistance to latch-up.
In the semiconductor device of the fifth aspect, the first and second MOS transistors are disposed so that these are isolated from each other, and the first MOS transistor is disposed in the high side region surrounded by the first trench isolation wall and the second MOS transistor is surrounded by the second trench isolation wall so that these transistors are electrically isolated. Therefore, holes and electrons that are carriers constituting the main current of the first and second MOS transistors are isolated from one another by the isolation structure, and an occurrence of modulation can be suppressed even if holes and electrons are obtained at a high density. Further, since the first and second MOS transistors are isolated for electrical isolation, no parasitic thyristor structure is present and latch-up can be principally prevented to allow for an improvement in resistance to latch-up. Furthermore, since the first MOS transistor is formed in the high side region, it is unnecessary to provide a trench isolation wall for electrically isolating the first MOS transistor, thereby increasing the integration degree of the semiconductor device.
In the semiconductor device of the sixth aspect, the first and second MOS transistors are disposed so that these are isolated from each other, and the first MOS transistor is buried in the first trench isolation wall in the high side region surrounded by the first trench isolation wall so that it is electrically isolated. Therefore, holes and electrons that are carriers constituting the main current of the first and second MOS transistors are isolated from one another by the isolation structure, and an occurrence of modulation can be suppressed even if holes and electrons are obtained at a high density. Further, since the first and second MOS transistors are isolated for electrical isolation, no parasitic thyristor structure is present and latch-up can be principally prevented to allow for an improvement in resistance to latch-up. Furthermore, since the first MOS transistor is disposed so as to be buried in the first trench isolation wall, the area occupied by the first MOS transistor is reduced to increase the integration degree of the semiconductor device.
In the semiconductor device of the seventh aspect, when a forward blocking voltage is applied, the field occurred between the first and second main electrodes is distributed through the inner wall oxide film of each trench constituting the side surface isolation wall, and the field is distributed substantially uniformly between the first and second main electrodes of the first MOS transistor. Thereby, no field concentration is present on the side surface isolation wall and the field concentration can be relaxed to stabilize breakdown voltage characteristic.
In the semiconductor device of the eighth aspect, the plural second trenches are arranged so as to block the end portion of the SOI layer interposing the plural first trenches, and the inner wall oxide film of the first trenches and that of the second trenches are joined and integral with each other. It is therefore avoided that during on-operation, carriers moving between the first and second main electrodes of the first MOS transistor are diffused into the SOI layer among the plural first trenches, thereby preventing an increase in switching loss.
In the semiconductor device of the ninth aspect, the main current of the first MOS transistor passes from the second main electrode to the first main electrode of the second MOS transistor via the first and second resistance components. During this, when the potential difference occurred in the first and second resistance components becomes a predetermined value, the control electrode of the second MOS transistor is controlled thereby to control on-off operation of the second MOS transistor.
It is an object of the present invention to overcome the foregoing drawback by providing a DAD that improves resistance to latch-up and stabilizes breakdown voltage characteristic.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.